IA. Field of the Invention
This invention relates to reduction of power consumption for sequential circuits. Specifically, this invention relates to a system and method for reducing power consumption. This invention is embodied in a controller-based power management system, in a method for managing power consumption in a sequential circuit and in a computer product that enables a computer to perform according to the method.
IB. Related Work
Power consumption in CMOS circuits is dominated by the dynamic component that is incurred whenever signals in such circuits undergo logic transitions. However, in practice it is found that some large portions of such logic transitions that occur in a circuit are unnecessary. These unnecessary logic transitions do not affect the value generated at the circuit output. As a result, all parts of a circuit need not function in each clock cycle.
Several conventional techniques have been used to reduce power consumption in a circuit by eliminating unnecessary logic transitions at various signals within the circuit. The term "power management" is collectively used to refer to these techniques.
Conventional techniques called sequential circuit power management techniques have been applied for designing circuits at the logic and also architecture levels. Some of these techniques either involve gating clocks or preventing flip-flops/registers from being loaded to save power consumption. In such techniques, savings occur in the clock tree as well as the logic fed by the flip-flops.
Another class of techniques is called combinational circuit power management. Here again, the technique is applied at the logic and architecture levels. Combinational techniques identify idle parts of a circuit called "sub-circuits under power management" (SUPs) within the same clock cycle and shut them down.
Most modern microprocessors and microcontrollers that target portable applications employ the strategy of gating the clock input to registers in a circuit / non-overlapping clocks has been used conventionally to reduce power consumption. See C. Papachristou, M. Spining, and M. Nourani, "An effective Power Management Scheme for RTL Design Based on Multiple Clocks," in Proc. Design Automation Conf., pp. 337-342, June 1996.
In another power optimization technique the output of a logic block is precomputed one or more cycles in advance. The output of a logic block, and the precomputed information is used to disable registers at the input of the blocks being loaded in future cycles. See M. Aldina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, "Precomputation-Based Sequential Logic Optimization for Low Power," in IEEE Trans. VLSI Systems, vol. 2, pp. 426-436, December 1994.
Conventionally designers have also used the idea of avoiding unnecessary transitions to logic blocks whose inputs are not fed by registers, by inserting "signal barriers" such as pass transistors or transparent latches. See M. Aldina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, "Precomputation-Based Sequential Logic Optimization for Low Power," in IEEE Trans. VLSI Systems, vol. 2, pp. 426-436, December 1994 and V. Tiwari, S. Malik, and P. Ashar, "Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design," in Proc. Int. Symp. Low Power Design, pp. 221-226, April 1995 and A. Correale Jr., "Overview of the Power Minimization Techniques Employed in the IBM PowerPC 4xx Embedded Processors," in Proc. Int. Symp. Low Power Design, pp. 75-80, April 1995.
Yet another technique suggested in literature is an automated technique called guarded evaluation. Here, parts of a circuit that can be isolated or shut off for each cycle is determined. See V. Tiwari, S. Malik, and P. Ashar, "Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design," in Proc. Int. Symp. Low Power Design, pp. 221-226, April 1995.
The notion of operand isolation has also been integrated into high-level synthesis. Here, transparent latches are inserted at the inputs of each functional unit in order to freeze the previous cycle's values in control steps of the schedule where the functional unit is unused. See E. Musoll and J. Cortadella, "High-Level Synthesis Techniques for Reducing the Activity of Functional Units," in Proc. Int. Symp. Low Power Design, pp. 99-104, April 1995.
An approach to perform scheduling during high-level synthesis to maximize the opportunities for pre-computation was presented in J. Monteiro, P. Ashar, and S. Devadas, "Scheduling Techniques to Enable Power Management," in Proc. Design Automation Conf, pp. 349-352, June 1996. Software and firmware-controlled power management are already a commercial practice as suggested by products such as Fujitsu's SPARClite microprocessor, and Phoenix Technologies NoteBIOS 4.0.
The evolution of high-level design techniques where the above-mentioned power management techniques have been used has often been driven by specific application domains, such as data-flow or control-flow. Data-flow is often an arithmetic intensive domain that includes digital signal processing, image processing, graphics, and several multimedia applications. However, control-flow is often a decision intensive application domain, that includes networking/telecommunication protocols, embedded controllers, etc.
The behavioral descriptions of data-flow intensive designs are dominated by arithmetic operations such as addition, subtraction, and multiplication. On the other hand, the behavioral descriptions of control-flow intensive designs are dominated by nested conditional constructs, data-dependent loops, and comparisons, with very few arithmetic operations.
Area, delay, and power of structural RTL implementations of data-flow intensive designs are dominated by arithmetic units and registers in the data path. On the other hand, area, delay and power of control-flow intensive designs are dominated by non-arithmetic units like multiplexers, bit-manipulation units, and comparators.
A large number of designs, in practice, are control-flow intensive. A substantial number of designs contain a significant mix of control and data flow.
Control-flow intensive designs have several characteristics that pose challenges to conventional power management techniques:
Power consumption is dominated by an abundance of smaller components like multiplexers, while functional units may account only for a small part of the total power. See A. Raghunathan, S. Dey, and N. K. Jha, "Glitch Analysis and Reduction in Register-Transfer-Level Power Optimization," in Proc. Design Automation Conf, pp. 331-336, June 1996. In such circuits addition to power overheads due to the insertion of transparent latches is comparable to power savings obtained when power management is applied to sub-circuits such as multiplexer networks. PA1 Signals that detect idle conditions for various sub-circuits are typically late-arriving (for example, due to the presence of nested conditionals within each controller state, the idle conditions may depend on outputs of comparators from the data path). As a result, timing constraints that must be imposed to apply conventional power management techniques are often not met because the "enable" signal to the transparent latches must settle before its data inputs can change. PA1 The presence of significant glitching activity at control as well as data path signals needs to be accounted for in order to obtain maximal power savings. See A. Raghunathan, S. Dey, and N. K. Jha, "Glitch Analysis and Reduction in Register-Transfer-Level Power Optimization," in Proc. Design Automation Conf, pp. 331-336, June 1996. PA1 A significant amount of power consumed in sequential circuits is unnecessary. PA1 Conventional techniques do not achieve as much power reduction as can be achieved with the current state of technology. PA1 Conventional power management techniques cause circuit delay. PA1 Conventional power management techniques cause glitching activity at control and data path signals. PA1 Conventional power management techniques cause formation of false combinational cycles. PA1 Conventional power management techniques may not be suited for control-flow intensive designs.
These problems reveal that conventional power management techniques may often not be suited to control-flow intensive designs. On the other hand, they cause negative effects like circuit delay, glitching activity at control and data path signals, and formation of false combinational cycles.
Though several techniques have been used in conventional systems as noted above, significant reductions in power consumption in data-flow and control-flow still needs to be achieved. Power consumption should be reduced further to realize the potential offered by sequential circuits in the design of products used daily. For example, reductions in power consumption are required for further miniaturization of appliances like personal computers, remote control devices, etc.
The following problems, at least, exist in conventional sequential circuit design techniques: